View UPD161643P_1522614.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

2001 mos integrated circuit pd161643 176-output tft-lcd gate driver data sheet document no. s15796ej1v0ds00 (1st edition) date published february 2003 ns cp(k) printed in japan the mark shows major revised points. the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. description the pd161643 is a tft-lcd gate driver. because this gate driver has a level shift circuit for logic input, it can output a high gate scanning voltage in response to a cmos-level input. features ? high-withstanding-voltage output (v t -v ee = 42 v max.) ? 3.0 v cmos level input ? number of output: 176 ordering information part number package pd161643p chip remark purchasing the above chip entails the exchange of documents such as a separate memorandum or product quality, so please contact one of our sales representatives.
data sheet s15796ej1v0ds 2 pd161643 1. block diagram sr1 sr2 sr87 mpx sr88 sr89 sr90 sr175 sr176 v ee v ss v cc1 v t stvl o 175 o 176 o 1 o 2 r,/l clk stvr oe2 oe1 v b level shifter o 89 o 90 o 87 o 88 pv ss pv cc1 stvsel oe1sel oe2sel remark /xxx indicates active low si gnal.
data sheet s15796ej1v0ds 3 pd161643 2. pin configuration (pad layout) chip size: 2.3 x 7.05 mm 2 bump size: input/left/right (include input/output/right side dummy): 49 x 85 m 2 output (include output side dummy): 35 x 94 m 2 no.285 no.1 no.283 no.284 no.94 no.96 no.95 face up x y 30 m 30 m 30 m 30 m 30 m 30 m 10 m no.93 alignment mark 1 alignment mark 1 alignment mark 2 alignment mark 2 alignment mark 1 10 m 10 m 10 m 10 m 10 m (0, 0)
data sheet s15796ej1v0ds 4 pd161643 table 2 ? ? ? ? 1. pad layout (1/4) pad no. pad name x [mm] y [mm] pad no. pad name x [mm] y [mm] - alignment mark1 -0.9995 -3.3745 66 vee -0.9995 1.3300 67 vee -0.9995 1.4000 1 dummy -0.9995 -3.2200 68 vee -0.9995 1.4700 2 dummy -0.9995 -3.1500 69 dummy -0.9995 1.5400 3 dummy -0.9995 -3.0800 70 dummy -0.9995 1.6100 4 dummy -0.9995 -3.0100 71 vb -0.9995 1.6800 5 dummy -0.9995 -2.9400 72 vb -0.9995 1.7500 6 dummy -0.9995 -2.8700 73 vb -0.9995 1.8200 7 dummy -0.9995 -2.8000 74 vb -0.9995 1.8900 8 dummy -0.9995 -2.7300 75 vb -0.9995 1.9600 9 dummy -0.9995 -2.6600 76 dummy -0.9995 2.0300 10 dummy -0.9995 -2.5900 77 dummy -0.9995 2.1000 11 dummy -0.9995 -2.5200 78 stvr -0.9995 2.1700 12 dummy -0.9995 -2.4500 79 stvr -0.9995 2.2400 13 dummy -0.9995 -2.3800 80 dummy -0.9995 2.3100 14 dummy -0.9995 -2.3100 81 stvl -0.9995 2.3800 15 dummy -0.9995 -2.2400 82 stvl -0.9995 2.4500 16 dummy -0.9995 -2.1700 83 dummy -0.9995 2.5200 17 dummy -0.9995 -2.1000 84 clk -0.9995 2.5900 18 dummy -0.9995 -2.0300 85 clk -0.9995 2.6600 19 dummy -0.9995 -1.9600 86 dummy -0.9995 2.7300 20 dummy -0.9995 -1.8900 87 oe1 -0.9995 2.8000 21 dummy -0.9995 -1.8200 88 oe1 -0.9995 2.8700 22 dummy -0.9995 -1.7500 89 dummy -0.9995 2.9400 23 dummy -0.9995 -1.6800 90 oe2 -0.9995 3.0100 24 dummy -0.9995 -1.6100 91 oe2 -0.9995 3.0800 25 dummy -0.9995 -1.5400 92 dummy -0.9995 3.1500 26 dummy -0.9995 -1.4700 93 dummy -0.9995 3.2200 27 dummy -0.9995 -1.4000 28 pvcc1 -0.9995 -1.3300 - alignment mark1 -0.9995 3.3745 29 oe1sel -0.9995 -1.2600 30 oe1sel -0.9995 -1.1900 31 pvss -0.9995 -1.1200 32 oe2sel -0.9995 -1.0500 33 oe2sel -0.9995 -0.9800 34 pvcc1 -0.9995 -0.9100 35 stvsel -0.9995 -0.8400 36 stvsel -0.9995 -0.7700 37 pvss -0.9995 -0.7000 38 r,/l -0.9995 -0.6300 39 r,/l -0.9995 -0.5600 40 pvcc1 -0.9995 -0.4900 41 dummy -0.9995 -0.4200 42 dummy -0.9995 -0.3500 43 vt -0.9995 -0.2800 44 vt -0.9995 -0.2100 45 vt -0.9995 -0.1400 46 vt -0.9995 -0.0700 47 vt -0.9995 0.0000 48 dummy -0.9995 0.0700 49 dummy -0.9995 0.1400 50 vcc1 -0.9995 0.2100 51 vcc1 -0.9995 0.2800 52 vcc1 -0.9995 0.3500 53 vcc1 -0.9995 0.4200 54 vcc1 -0.9995 0.4900 55 dummy -0.9995 0.5600 56 dummy -0.9995 0.6300 57 vss -0.9995 0.7000 58 vss -0.9995 0.7700 59 vss -0.9995 0.8400 60 vss -0.9995 0.9100 61 vss -0.9995 0.9800 62 dummy -0.9995 1.0500 63 dummy -0.9995 1.1200 64 vee -0.9995 1.1900 65 vee -0.9995 1.2600 gate in p uts 70
data sheet s15796ej1v0ds 5 pd161643 table 2 ? ? ? ? 1. pad layout (2/4) pad no. pad name x [mm] y [mm] pad no. pad name x [mm] y [mm] 96 dummy 0.8650 3.2725 161 o117 0.9950 0.9975 97 dummy 0.9950 3.2375 162 o116 0.8650 0.9625 98 dummy 0.8650 3.2025 163 o115 0.9950 0.9275 99 dummy 0.9950 3.1675 164 o114 0.8650 0.8925 100 dummy 0.8650 3.1325 165 o113 0.9950 0.8575 101 dummy 0.9950 3.0975 166 o112 0.8650 0.8225 102 o176 0.8650 3.0625 167 o111 0.9950 0.7875 103 o175 0.9950 3.0275 168 o110 0.8650 0.7525 104 o174 0.8650 2.9925 169 o109 0.9950 0.7175 105 o173 0.9950 2.9575 170 o108 0.8650 0.6825 106 o172 0.8650 2.9225 171 o107 0.9950 0.6475 107 o171 0.9950 2.8875 172 o106 0.8650 0.6125 108 o170 0.8650 2.8525 173 o105 0.9950 0.5775 109 o169 0.9950 2.8175 174 o104 0.8650 0.5425 110 o168 0.8650 2.7825 175 o103 0.9950 0.5075 111 o167 0.9950 2.7475 176 o102 0.8650 0.4725 112 o166 0.8650 2.7125 177 o101 0.9950 0.4375 113 o165 0.9950 2.6775 178 o100 0.8650 0.4025 114 o164 0.8650 2.6425 179 o99 0.9950 0.3675 115 o163 0.9950 2.6075 180 o98 0.8650 0.3325 116 o162 0.8650 2.5725 181 o97 0.9950 0.2975 117 o161 0.9950 2.5375 182 o96 0.8650 0.2625 118 o160 0.8650 2.5025 183 o95 0.9950 0.2275 119 o159 0.9950 2.4675 184 o94 0.8650 0.1925 120 o158 0.8650 2.4325 185 o93 0.9950 0.1575 121 o157 0.9950 2.3975 186 o92 0.8650 0.1225 122 o156 0.8650 2.3625 187 o91 0.9950 0.0875 123 o155 0.9950 2.3275 188 o90 0.8650 0.0525 124 o154 0.8650 2.2925 189 o89 0.9950 0.0175 125 o153 0.9950 2.2575 190 o88 0.8650 -0.0175 126 o152 0.8650 2.2225 191 o87 0.9950 -0.0525 127 o151 0.9950 2.1875 192 o86 0.8650 -0.0875 128 o150 0.8650 2.1525 193 o85 0.9950 -0.1225 129 o149 0.9950 2.1175 194 o84 0.8650 -0.1575 130 o148 0.8650 2.0825 195 o83 0.9950 -0.1925 131 o147 0.9950 2.0475 196 o82 0.8650 -0.2275 132 o146 0.8650 2.0125 197 o81 0.9950 -0.2625 133 o145 0.9950 1.9775 198 o80 0.8650 -0.2975 134 o144 0.8650 1.9425 199 o79 0.9950 -0.3325 135 o143 0.9950 1.9075 200 o78 0.8650 -0.3675 136 o142 0.8650 1.8725 201 o77 0.9950 -0.4025 137 o141 0.9950 1.8375 202 o76 0.8650 -0.4375 138 o140 0.8650 1.8025 203 o75 0.9950 -0.4725 139 o139 0.9950 1.7675 204 o74 0.8650 -0.5075 140 o138 0.8650 1.7325 205 o73 0.9950 -0.5425 141 o137 0.9950 1.6975 206 o72 0.8650 -0.5775 142 o136 0.8650 1.6625 207 o71 0.9950 -0.6125 143 o135 0.9950 1.6275 208 o70 0.8650 -0.6475 144 o134 0.8650 1.5925 209 o69 0.9950 -0.6825 145 o133 0.9950 1.5575 210 o68 0.8650 -0.7175 146 o132 0.8650 1.5225 211 o67 0.9950 -0.7525 147 o131 0.9950 1.4875 212 o66 0.8650 -0.7875 148 o130 0.8650 1.4525 213 o65 0.9950 -0.8225 149 o129 0.9950 1.4175 214 o64 0.8650 -0.8575 150 o128 0.8650 1.3825 215 o63 0.9950 -0.8925 151 o127 0.9950 1.3475 216 o62 0.8650 -0.9275 152 o126 0.8650 1.3125 217 o61 0.9950 -0.9625 153 o125 0.9950 1.2775 218 o60 0.8650 -0.9975 154 o124 0.8650 1.2425 219 o59 0.9950 -1.0325 155 o123 0.9950 1.2075 220 o58 0.8650 -1.0675 156 o122 0.8650 1.1725 221 o57 0.9950 -1.1025 157 o121 0.9950 1.1375 222 o56 0.8650 -1.1375 158 o120 0.8650 1.1025 223 o55 0.9950 -1.1725 159 o119 0.9950 1.0675 224 o54 0.8650 -1.2075 160 o118 0.8650 1.0325 225 o53 0.9950 -1.2425 gate out p uts 35
data sheet s15796ej1v0ds 6 pd161643 table 2 ? ? ? ? 1. pad layout (3/4) pad no. pad name x [mm] y [mm] 226 o52 0.8650 -1.2775 227 o51 0.9950 -1.3125 228 o50 0.8650 -1.3475 229 o49 0.9950 -1.3825 230 o48 0.8650 -1.4175 231 o47 0.9950 -1.4525 232 o46 0.8650 -1.4875 233 o45 0.9950 -1.5225 234 o44 0.8650 -1.5575 235 o43 0.9950 -1.5925 236 o42 0.8650 -1.6275 237 o41 0.9950 -1.6625 238 o40 0.8650 -1.6975 239 o39 0.9950 -1.7325 240 o38 0.8650 -1.7675 241 o37 0.9950 -1.8025 242 o36 0.8650 -1.8375 243 o35 0.9950 -1.8725 244 o34 0.8650 -1.9075 245 o33 0.9950 -1.9425 246 o32 0.8650 -1.9775 247 o31 0.9950 -2.0125 248 o30 0.8650 -2.0475 249 o29 0.9950 -2.0825 250 o28 0.8650 -2.1175 251 o27 0.9950 -2.1525 252 o26 0.8650 -2.1875 253 o25 0.9950 -2.2225 254 o24 0.8650 -2.2575 255 o23 0.9950 -2.2925 256 o22 0.8650 -2.3275 257 o21 0.9950 -2.3625 258 o20 0.8650 -2.3975 259 o19 0.9950 -2.4325 260 o18 0.8650 -2.4675 261 o17 0.9950 -2.5025 262 o16 0.8650 -2.5375 263 o15 0.9950 -2.5725 264 o14 0.8650 -2.6075 265 o13 0.9950 -2.6425 266 o12 0.8650 -2.6775 267 o11 0.9950 -2.7125 268 o10 0.8650 -2.7475 269 o9 0.9950 -2.7825 270 o8 0.8650 -2.8175 271 o7 0.9950 -2.8525 272 o6 0.8650 -2.8875 273 o5 0.9950 -2.9225 274 o4 0.8650 -2.9575 275 o3 0.9950 -2.9925 276 o2 0.8650 -3.0275 277 o1 0.9950 -3.0625 278 dummy 0.8650 -3.0975 279 dummy 0.9950 -3.1325 280 dummy 0.8650 -3.1675 281 dummy 0.9950 -3.2025 282 dummy 0.8650 -3.2375 283 dummy 0.9950 -3.2725 gate out p uts 35
data sheet s15796ej1v0ds 7 pd161643 table 2 ? ? ? ? 1. pad layout (4/4) pad no. pad name x [mm] y [mm] pad no. pad name x [mm] y [mm] 94 dummy -0.3000 3.3925 284 dummy 0.3000 -3.3925 95 dummy 0.3000 3.3925 285 dummy -0.3000 -3.3925 pad no. pad name x [mm] y [mm] - alignment mark2 0.9950 -3.3925 gate left 600
data sheet s15796ej1v0ds 8 pd161643 3. pin functions (1/2) symbol pin name pad no. i/o function o 1 to o 176 driver output 277 to 102 output scan signal output pins that drive the gate electrode of a tft- lcd. the status of each output pin changes in synchronization with the rising edge of shift clock. the output voltage of the driver is v t -v b . stvr, stvl start pulse input/output 78, 79, 81, 82 i/o input/output pin of the internal shift register. read of start pulse signal is set at rising (or falling) edge of shift clock, and outputs a scanning signal from a driver output pin. in addition, the effective level of a stvr/stvl pin is determined by setup of stvsel pin. moreover, an input/output level is v cc1 - v ss (logic level). stvsel = l: start pulse is set to low level by the 176th falling edge of shift clock, and is set to a high level by the 177th falling edge. stvsel start pulse input effective level selection 35, 36 input the effective level of the start pulse signal inputted into stvr/stvl is selected. stvsel = l: low level stvsel = h: high level clk shift clock input 84, 85 input shift clock input for the internal shift register. the contents of internal shift register is shifted at the rising edge of clk. connect to gclk pin of source driver. r,/l shift direction switching input 38, 39 input shift direction switching input pin of the internal shift register. r,/l = h (right shift): stvr o 1 o 2 o 175 o 176 stvl r,/l = l (left shift): stvl o 176 o 175 o 2 o 1 stvr oe1 enable input 87, 88 input input of the level selected by oe1sel fixes a driver output to a low level (input of a low level fixes driver output to low level at the time of oe1sel = l). however, shift register is not cleared. moreover, output enable operation is asynchronous on a clock. connect with goe1 pin of sauce driver. oe1sel oe1 effective level selection 29, 30 input this pin selects effective level of oe1 pin. oe1sel = l: low level oe1sel = h: high level oe2 enable input 90, 91 input input of the level selected by oe2sel fixes a driver output to a high level (input of a low level fixes driver output to high level at the time of oe2sel = l). however, shift register is not cleared. moreover, output enable operation is asynchronous on a clock. connect with goe2 pin of sauce driver. oe2sel oe2 effective level selection 32, 33 input this pin selects effective level of oe2 pin. oe2sel = l: low level oe2sel = h: high level
data sheet s15796ej1v0ds 9 pd161643 (2/2) symbol name pad no. i/o function v t positive power supply for driver 43 to 47 ? positive power supply for level shifter and output buffer. positive power supply for liquid crystal. v ee negative power supply for logic 64 to 68 ? negative power supply for level shifter. v b negative power supply for driver 71 to 75 ? negative power supply for output buffer. negative power supply for liquid crystal. v cc1 positive power supply for logic 50 to 54 ? positive power supply for logic circuit. v ss ground 57 to 61 ? connect to the system ground. pv cc1 pull-up power supply 28, 34, 40 ? pull-up power supply for mode setting pins (r,/l, stvsel, oe1sel, oe2sel). pv ss pull-down power supply 31, 37 ? pull-down power supply for mode setting pins (r,/l, stvsel, oe1sel, oe2sel). 4. mode description output mode selection r,/l stvr stvl scan direction h input output 1 176 l output input 176 1 remark h: v cc1 , l: v ss
data sheet s15796ej1v0ds 10 pd161643 5. timing chart the timing chart in each condition is shown as follows. r,/l = h, stvsel = l, oe1sel = l, oe2sel = l clk oe1 oe2 stvr o 1 o 2 o 3 o 176 stvl (o 1 ) (o 2 ) (o 3 ) 1 23 4 176 177 178 179 180 181 r,/l = l, stvsel = h, oe1sel = h, oe2sel = h clk oe1 oe2 stvl o 176 o 175 o 174 o 1 stvr (o 176 ) (o 175 ) (o 174 ) 176 177 178 179 1 2 3 4 181 180
data sheet s15796ej1v0ds 11 pd161643 r,/l = h, stvsel = h, oe1sel = l, oe2sel = h clk oe1 oe2 stvr o 1 o 2 o 3 o 176 stvl (o 1 ) (o 2 ) (o 3 ) 1 23 4 176 177 178 179 180 181 r,/l = l, stvsel = h, oe1sel = h, oe2sel = l clk oe1 oe2 stvl o 176 o 175 o 174 o 1 stvr (o 176 ) (o 175 ) (o 174 ) 176 177 178 179 1 2 3 4 181 180
data sheet s15796ej1v0ds 12 pd161643 6. electrical specifications absolute maximum ratings (t a = 25 c, v ss = 0 v) parameter symbol rating unit supply voltage v t ?0.5 to +30 v supply voltage v cc1 ?0.5 to +6.5 v supply voltage v t -v ee ?0.5 to +45 v supply voltage v ee ? 25 to +0.5 v supply voltage v b v ee ? 0.5 to +0.5 v input voltage note v i ? 0.5 to v cc1 + 0.5 v operating ambient temperature t a ? 40 to +85 c storage temperature t stg ? 55 to +150 c note r,/l, clk, stvr, stvl, oe1, oe2, stvsel, oe1sel, oe2sel caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. recommended operating conditions (t a = ?40 to +85 c, v ss = 0 v) parameter symbol min. typ. max. unit supply voltage v t 10 15 25 v supply voltage v ee ?20 ?15 ?10 v supply voltage v b v ee ?15 ?6.5 v supply voltage v t -v ee 20 30 42 v supply voltage v cc1 2.5 3.0 3.6 v input voltage note v i 0v cc1 v note r,/l, clk, stvr, stvl, oe1, oe2, stvsel, oe1sel, oe2sel
data sheet s15796ej1v0ds 13 pd161643 electrical characteristics (t a = ? ? ? ? 40 to +85 c, v cc1 = 2.5 to 3.6 v, v t = 15 v, v ee = v b = ? ? ? ? 15 v, v ss = 0 v) parameter symbol condition min. typ. max. unit high level input voltage v ih1 0.8 v cc1 v cc1 v low level input voltage v il1 r,/l, clk, stvr, stvl, oe1, oe2, stvsel, oe1sel, oe2sel 00.2 v cc1 v high level output voltage v oh stvr, stvl, i oh = ?40 av cc1 ? 0.4 v cc1 v low level output voltage v ol stvr, stvl, i oh = +40 a0 0.4v r on1 o 1 to o 176 , v out = v t ? 0.5 v 5.0 7.5 k ? output on resistance r on2 o 1 to o 176 , v out = v ee + 0.5 v 5.0 7.5 k ? input current i i1 logic input pin 1.0 a dynamic current 1 i cc1 v cc1 , note 200 a dynamic current 2 i t v t , note 100 a dynamic current 3 i ee v ee , note 100 a static current note i ss v cc1 , v t in stand-by mode 10 a note f clk = 20 khz, frame frequency = 60 hz, output no load switching characteristics (t a = ? ? ? ? 40 to +85 c, v cc1 = 2.5 to 3.6 v, v t = 15 v, v ee = v b = ? ? ? ? 15 v, v ss = 0 v) parameter symbol condition min. typ. max. unit t phl1 800 ns cascade output delay time t plh1 c l = 20 pf, clk stvl (stvr) 800 ns t phl2 1.5 s driver output delay time 1 t plh2 c l = 50 pf, clk o n 1.5 s t phl3 1.5 s driver output delay time2 t plh3 c l = 50 pf, oe1 on 1.5 s t phl4 1.5 s driver output delay time 3 t plh4 c l = 50 pf, oe2 on 1.5 s output rise time t tlh 1.5 s output fall time t thl c l = 50 pf 1.5 s input capacitance c i t a = 25 c15pf clock frequency f clk when connected in cascade 20 100 khz timing requirement (t a = ? ? ? ? 40 to +85 c, v cc1 = 2.5 to 3.6 v, v t = 15 v, v ee = v b = ? ? ? ? 15 v, v ss = 0 v) parameter symbol condition min. typ. max. unit clock pulse high period pw clk(h) 500 ns clock pulse low period pw clk(l) 500 ns enable pulse high period pw oe oe1, oe2 1 s data setup time t setup stvr (stvl) clk 200 ns data hold time t hold clk stvr (stvl) 200 ns remark the rise and fall times of logic input must be t r = t f = 20 ns (10 to 90%)
data sheet s15796ej1v0ds 14 pd161643 switching characteristics waveform (r,/l = h, stvsel = l, oe1sel = l, oe2sel = l) clk ( ): r,/l = l v cc1 v ss stvr (stvl) v cc1 v ss stvl (stvr) v cc1 v ss oe1 v cc1 v ss o n v t v b 1/f clk pw clk(h) pw clk(l) 50% 50% 50% 50% t setup t hold 50% 50% t plh1 t phl1 50% 50% t plh2 t tlh t phl2 t thl 90% 90% 10% 10% pw oe 50% 50% t phl3 t plh3 10% 90% o n v t v b oe2 v cc1 v ss o n v t v b pw oe 50% 50% t plh4 t phl4 90% 10%
data sheet s15796ej1v0ds 15 pd161643 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
pd161643 reference documents nec semiconductor device reliability/quality control system (c10983e) quality grades on nec semiconductor devices (c11531e) the information in this document is current as of february, 2003. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer- designated "quality assurance program" for a specific application. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) (1) "nec electronics" as used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. (2) "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). ? ? ? ? ? ? m8e 02. 11-1

▲Up To Search▲

Price & Availability of UPD161643P

	To Download UPD161643P Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .